1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, more particularly to a method for forming metallic wirings of a semiconductor device through polishing and a semiconductor device manufactured using the method.
2. Description of the Related Art
In recent years, planarization of the surfaces of wiring boards has been increasingly valued for large scale semiconductor integrated circuits (LSIs). One of the representative techniques for such the planarization is the Chemical Mechanical Polishing (CMP: hereafter, to be described as polishing otherwise specially defined), which is disclosed in, for example, the U.S. Pat. No. 4944836. According to this method, for example, a metal film for wiring is formed on a silicon substrate (wiring board) on which an LSI is to be formed, then the metal film is treated through well-known lithography and Reactive Ion Etching (RIE) techniques, thereby forming the object wiring pattern. After that, an insulating layer is formed on the wiring pattern. If the surface of the insulating layer is planarized through polishing, the fabrication accuracy of the wiring to be formed in the upper layer will be improved more effectively.
On the other hand, the damascene method that forms metallic wirings through polishing steps is also a focus of attention. According to the damascene method, an insulating film is formed on a wiring board at first, then grooves are formed in the insulating film for the wiring using both well-known lithography and RIE techniques. On the board with those grooves is then deposited a metal film for wiring. After that, the metal film except for the portion inlaid in each groove is removed through polishing, so that inlaid metal lines are formed there. This technique is disclosed in, for example, Japanese Patent Laid-Open No.2-278822. This method, which is effective especially when lines are to be formed with a copper based alloy whose fine fabrication by RIE is difficult, is also now under study as a method for fine fabrication of aluminum wiring patterns.
The details of the conventional damascene method are introduced in the official gazette of Japanese Patent Laid-Open No.10-214834 and in the publication of Proceedings CMP-MIC Conference (pp.415-422). Those examples describe a layered film consisting of tungsten and titanium respectively. Hereunder, the damascene method will be described on the basis of those examples with reference to FIG. 3. At first, an insulating layer 31 is formed on a wiring board 30 as shown in FIG. 3(a). Then, in the insulating layer 31 are formed depressions such as grooves or holes (to be referred to as grooves 32 generically) to be used as wirings and interlevel portions. After that, a lower metallic layer 32 and an upper metallic layer 33 are formed in order so as to cover the insulating layer 31. The lower metallic layer 32 consists of titanium and the lower metallic layer 33 consists of tungsten.
After that, both upper and lower metallic layers 32 and 33 except for the grooves are removed through polishing as shown in FIG. 3(b). Since the upper metallic layer 33 to be polished in the dense area of each groove pattern is substantially thinner than that of other areas provided with no pattern, the polishing of the upper metallic layer 33 is ended earlier in the pattern dense area than in other non-pattern areas. Therefore, when the lower metallic layer 32 and the first insulating layer 31 are exposed, part 33a of the upper metallic layer 33 still remains unfinished in each no-pattern area. And, if the polishing is continued until the lower metallic layer 32 is removed completely, phenomena referred to as erosion and dishing occur. The erosion means a phenomenon that the surface of the insulating layer 31 is depressed by a depth E1 more in each pattern dense area than in other non-pattern areas as shown in FIG.(c). The dishing means a phenomenon that the surface of the upper metallic layer 33 is depressed by a depth D1 more in each groove from the surface of the surrounding insulating layer 31. It is also reported that a localized erosion occurs at a depth of LE especially at each boundary between a pattern dense area and a no-pattern area. It is also reported that this localized erosion depends on the relative moving directions of both polishing platen and wiring board, as well as the type of the polishing pad, etc.
The reason why such a height difference occurs is explained as follows. Generally, a polishing agent for the layered metals causes the polishing rate to be reduced in order of upper metallic layer, lower metallic layer, and insulating layer. In particular, a significant difference appears between polishing rates for the lower metallic layer and the insulating layer. In most cases, the polishing rate of the insulating layer is only a factor of scores with respect to the polishing rate for the lower metallic layer. Since the polishing rates for the upper and lower metallic layers 32 and 33 are larger than that of the insulating layer such way, the surfaces of the upper and lower metallic layers 32 and 33 in each pattern dense area are depressed deeply from the surface for the insulating layer 31 when the polishing ends. Consequently, a large polishing force is concentrated effectively at each projection of the insulating layer 31.
The polishing of the insulating layer is thus accelerated in each pattern dense area according to this difference between such the polishing forces, thereby causing a large height difference. And, a total of such an erosion depth E1, a localized erosion depth LE, and a dishing depth D1 would often reach 1/2 of the initial depth of the groove. If an inlaid metal is used for wiring, therefore, such a depth will increase the resistance of the object wiring significantly. In addition, if an attempt is made to form a multi-layered wiring on this layer using the damascene method, the height differences generated by such the erosion depth E1, the localized erosion depth LE, and the dishing depth D1 will affect the wiring in the upper layer, causing the metallic layer to be left unpolished in each depression. And, this unpolished portion of the metallic layer causes short-circuits of the wiring in the upper layer.
There is a two-step polishing method proposed for minimizing the difference between polishing rates effectively by eliminating height differences as described above. Concretely, the polishing is finished once after the polishing of the upper metallic layer 33 is almost finished as shown in FIG. 3(d). Since the polishing rate for tungsten is five times faster than that for titanium, the polishing can be finished before the titanium film is removed completely. Next, the polishing agent is changed to another that contains silica abrasive powder and potassium hydroxide or ammonium hydroxide, thereby polishing the titanium of the lower metallic layer 32. The use of this polishing agent can almost equalize the polishing rate between the insulating film 31 and titanium. The polishing method will thus reduce the erosion depth E2 and the dishing depth D2 as shown in FIG. 3(d), thereby improving the planarization of the surface of the layer. This conventional two-step polishing method aims at elimination of polishing non-uniformity caused by the polishing of an upper or middle layer (titanium containing nitrogen, if necessary) by stopping the polishing (the first polishing) on the surface of the titanium film, which is a lower metallic layer. The first polishing is donefor layers including a thick tungsten film, which is an upper metallic layer, as well as a middle titanium nitride layer. The conventional two-step polishing method further aims at actual reduction of the non-uniformity of polishing only in the second polishing of the lower metallic layer. In the second polishing, the polishing rates for both lower metallic layer and insulating layer should preferably be equal or over. Actually, however, the polishing rate for the insulating layer is faster than or almost equal to that for the lower metallic layer. The conventional two-step polishing method also aims at reduction of the dependency of the polishing rate on pattern by equalizing both polishing rates. According to this polishing method, therefore, the planarization of the surface of the insulating layer is improved after the polishing. More concretely, the polishing of the insulating layer is increased significantly. Consequently, the residual insulating film becomes thinner contrarily in some cases. However, since such a structure is used mainly as plugs for interlevel connection conventionally after tungsten is inlaid in the film, it has been considered that a metallic layer should rather be protruded from the insulating layer surface as disclosed in the official gazette of Japanese Patent Laid-Open No.9-167768. Such way, the planarization of the surface of the insulating layer has been considered to be important even when the insulating layer is thinned.
The official gazette of Japanese Patent Laid-Open No.8-83780 discloses a polishing method for copper based alloys. The gazette also describes a polishing method for a copper based alloy film and a tungsten film, as well as favorable characteristics of a polishing agent, which are obtained when the polishing agent contains alumina abrasive powder, a metallic layer oxidizer, and etching chemicals. Concretely, while the surface of an object metallic layer is oxidized using an oxidizer, the oxide is removed mechanically by abrasion due to the friction with inorganic abrasive powder and polishing pad. This is accepted as a basic polishing mechanism. The etching chemical is used to increase the polishing of metallic layers. If such the etching chemical is added to a polishing agent, however, etching also proceeds onto the metallic layer in each groove which comes in contact with neither abrasive powder nor polishing pad, thereby the planarization of the surface is degraded. In order to avoid such a problem, corrosion-proof agent, i.e., inhibitors are added to the polishing agent. Dishing can be prevented by increasing the ratio of the polishing rate to the etching rate, thereby improving the fabrication accuracy. In this example, the pH (hydrogen exponent) of the polishing agent is assumed to be neutral. If a corrosion-proof agent is added to the polishing agent, however, the polishing rate is lowered significantly. More concretely, if a corrosion-proof agent is added by 0.1%, the polishing rate is lowered down to 10 nm/min. Consequently, the ratio between polishing and etching rates is not always increased in proportion to the concentration of the corrosion-proof agent. Since the actual polishing rate must be 100 nm/min or so, such the characteristics will not be suitable for practical uses. In order to avoid occurrence of such a dishing phenomenon, there is also proposed a substantially two-step polishing method, which polishes a copper based alloy at the room temperature, then polishes a barrier layer mainly by lowering the temperatures of both polishing platen and polishing agent, thereby changing the polishing characteristics.
The following polishing agents available on the market are well known. QCTT1010 (a product of RODEL Inc., to be mixed with a hydrogen peroxide solution when used) contains alumina abrasive powder to function as a polishing agent for copper based alloys. And, the following are well known as polishing agents for tungsten: SS-W2000 (a product of CABOT Inc., to be mixed with a hydrogen peroxide solution when used) including silica abrasive powder, WA-400 (a product of CABOT Inc., to be mixed with an FE-400 solution including ferric nitride when used) including alumina abrasive powder, MSW-1000 (a product of RODEL Inc., to be mixed with a hydrogen peroxide solution when used), XGB-5542 (a product of RODEL Inc., to be mixed with potassium iodate when used), etc. On the other hand, the polishing agents should preferably be alkaline in order to increase the polishing of the above-mentioned insulating film. Generally, each of those polishing agents contains silicon abrasive powder, ammonium hydroxide, and potassium hydroxide. Polishing of insulating films has been used for a long time and many products have appeared on the market. It is well known that the hydrogen exponent (pH) of the solution is changed depending on the concentration of ammonium hydroxide and potassium hydroxide, thereby the polishing characteristics are changed. In the official gazette of Japanese Patent Laid-Open No.10-214834, such a type polishing agent is used for polishing a titanium layer.
However, since this two-step polishing method makes the polishing rates for both lower metallic layer 32 and insulating layer 31 closer as described above with reference to FIG. 3, polishing of the insulating layer 31 is speeded up if a polishing agent in use consists of silica abrasive powder and an alkaline solution of potassium hydroxide, ammonium hydroxide, etc. Consequently, while the height difference on the surface of the insulating layer is reduced significantly, the no-pattern insulating layer 30 is also polished away when this method is used. The insulating film is thus thinned by a value .DELTA.T shown in FIG. 3(e). And, the total of the erosion E2, the dishing depth D2, and the reduction .DELTA.T in the film thickness will reduce each groove in depth significantly, as well as the inlaid metallic layer in thickness. The use of such an insulating layer for wiring will thus increase the resistance of the wiring. This is why the insulating film will not be satisfactory yet in quality.
The polishing rate for titanium used for the lower metallic layer 32 is actually almost the same as that for the insulating layer 30. The upper limit ratio between the polishing rates for both layers 32 and 30 is concretely described in the 0058 field as 120 nm/min for the polishing rate for titanium and 25 nm/min for the polishing rate for oxide films if potassium iodate is used for the polishing agent.
Consequently, the polishing rate for titanium becomes 4.8 times (120/25=4.8) that for oxide films. This polishing agent can be used as the first polishing agent. The second polishing agent should be another (0060 field), however. It will be understood therefore that the polishing rate of the second polishing agent for the lower metallic layer should preferably be almost equal to that for the insulating layer and must be not more than 4.8 times that for the insulating layer. In spite of this, if polishing is done excessively by ten or scores of % in consideration of the polishing rate distribution, the structure over a plurality of wiring boards, and the polishing rate variability in a large area wiring board, then the resistance of the wiring is varied significantly due to the variability of the grooves in depth in the wiring board, and by extension, due to the difference between the wiring layers in thickness. Thus, polishing selectivity for lower metallic layer, i.e., polishing rate ratio of that for lower metallic layer to that for the underlying insulating layer, of 4.8 or less will not be enough.
In order to form low-resistance wirings in uniform all over the surface of a wiring board, therefore, it is required to remove both upper and lower metallic layers from predetermined portions of the entire surface of the wiring board, for example, from the entire region in which wiring circuit elements are formed, without thinning the insulating layer 31 at all.
Under such the circumstances, it is an object of the present invention to form wirings by suppressing the degradation of their shapes so as to keep both yield and stability of the production satisfactorily when multilayered damascene wirings are formed by removing the first alloy layer. Each of the damascene wirings consists of an upper metallic layer, and a lower metallic layer which is effective as a barrier layer.
The official gazette of Japanese Patent Laid-Open No.10-214834 has never described chemical etching in polishing. It is thus unknown how much the etching proceeds chemically in the polishing process.